The present invention relates to a DA converter, and in particular to a low power consumption DA converter.
As high performance and low power consumption of large scale integration (LSI) are required, high performance (reduction in the amount of glitches) and low current consumption of DA converter are increasingly required. Generally, a current summing DA converter (for example, Japanese Unexamined Patent Application Publication No. Sho 62 (1987)-5729) is used as a DA converter in which the amount of glitches is reduced. However, an ordinary current summing DA converter has a problem that the current consumption is large. Therefore, a DA converter that can reduce current consumption is desired to be developed.
An example of the current summing DA converter as mentioned above will be described. FIG. 10 is a circuit block diagram showing a configuration of an eclectic DA converter 900 in which a current summing DA converter is mounted. As shown in FIG. 10, the eclectic DA converter 900 includes a driver unit 91, a segment decoder unit 92, an R-2R driver unit 93, a segment type (current summing) DA converter 94, and an R-2R resistance ladder DA converter 95. The eclectic DA converter 900 processes the upper m bits of inputted (m+n) bits (m and n are integers of 2 or more) by the segment type (current summing) DA converter 94 and processes the lower n bits by the R-2R resistance ladder DA converter 95. The upper m bits are inputted into the segment decoder unit 92 via the driver unit 91. The lower n bits are inputted into the R-2R resistance ladder DA converter 95 via the R-2R driver unit 93.
The segment decoder unit 92 has (2m−1) decoders (not shown in FIG. 10). Thereby, a digital signal of the upper m bits inputted into the segment decoder unit 92 is decoded into a signal of (2m−1) bits. The segment type DA converter 94A has (2m−1) current sources and current switches. The (2m−1) current sources (current value I0) and current switches are switched to an off state or an on state according to the signal of (2m−1) bits outputted from the segment decoder unit 92. Thereby, the digital signal of the upper m bits is converted into an analog amount in a range from 0 [V] to −(2m−1)×I0×(⅔)×R [V].
The R-2R resistance ladder DA converter 95 has n current sources (current value I0) and current switches, and a resistance ladder. The resistance ladder includes resistances R (resistance value is R) and resistances 2R (resistance value is 2R). Each of the n current sources and current switches is switched to an off state or an on state according to one bit of a lower n-bit signal. Thereby, the lower n-bit signal is converted into an analog amount in a range from 0 [V] to −(1−(½′))×I0×(⅔)×R [V] by the resistance ladder.
An analog output corresponding to a digital signal of (m+n) bits inputted into the eclectic DA converter 900 has an analog amount obtained by summing up the analog amounts generated by the segment type DA converter 94 and the R-2R resistance ladder DA converter 95.